`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   13:34:52 04/25/2013
// Design Name:   register_set
// Module Name:   C:/ASU/CSE320/Project3/tb_register_set.v
// Project Name:  Project3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: register_set
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_register_set;

	// Inputs
	reg [3:0] data;
	reg [1:0] addr;
	reg LDR;
	reg dis_read;
	reg [1:0] dis_addr;
	reg reset;
	reg clk;
	reg [7:0] ALU_data;
	reg alu_en;
	// Outputs
	wire [3:0] rega;
	wire [3:0] regb;
	wire [3:0] dis_data;

	// Instantiate the Unit Under Test (UUT)
	register_set uut (
		.data(data), 
		.addr(addr), 
		.LDR(LDR), 
		.dis_read(dis_read), 
		.dis_addr(dis_addr), 
		.reset(reset), 
		.clk(clk), 
		.alu_en(alu_en),
		.ALU_data(ALU_data), 
		.rega(rega), 
		.regb(regb), 
		.dis_data(dis_data)
	);

	initial begin
		// Initialize Inputs
		data = 0;
		addr = 0;
		LDR = 0;
		alu_en = 0;
		dis_read = 1;
		dis_addr = 0;
		reset = 0;
		clk = 0;
		ALU_data = 255;

		// Wait 100 ns for global reset to finish
		#10;
        
		// Add stimulus here
		forever #5 clk <= ~clk;
	end
   initial begin
		@(posedge clk) reset=1; ALU_data = 255; addr=0; data=0;
		#5
		/*test for data = a, addr = A, LDR = 1 */
		@(posedge clk) reset=1; ALU_data = 255; addr=2'b0; data=4'hA; 
		#5 LDR=1; 
		#10 LDR = 0; 
		#25
		/*test for data = c, addr = B, LDR = 1*/
		@(posedge clk) reset=1; ALU_data = 255; addr=2'b01; data=4'hC; 
		#5 LDR=1; 
		#10 LDR = 0;
		#25
		//ALU tests:
		/*test for write alu into D*/
		@(posedge clk)ALU_data = 14;addr=2'b11; 
		#5 alu_en = 1; 
		#10 alu_en = 0;
		#35
		
		/*test for destination B*/
		@(posedge clk)ALU_data = 5;  addr=2'b11; 
		#5 alu_en = 1;
		#10 alu_en = 0;
		#35
		/*test for destination A*/
		@(posedge clk)ALU_data = 8'h5f; addr = 2'b10;
		#5 alu_en = 1;
		#10 alu_en = 0;
		#35;
		$finish;
		
	end 
endmodule

